EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
EDN

Startup promises clean RTL code

San Jose, Calif. — Design automation startup Stelar Tools Inc. claims that its first product will cut 30 percent off the time it takes to move a design from initial RTL code development to synthesis.
Design-Reuse

Concept Engineering Introduces RTLvision PRO to Help Designers of IP-based System-on-Chip Reach Faster RTL Code Closure

FREIBURG, Germany - July 6, 2006 - Concept Engineering today announced the release of RTLvision¢â PRO, a customizable tool to help designers of intellectual property (IP)-based system-on-chip reduce ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Design-Reuse

Tensilica Announces Major IC Design Automation Breakthrough, The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code

SANTA CLARA, Calif. - Sept. 6, 2004 - Tensilica(R), Inc. today announced that it has achieved a major design automation breakthrough - the automated design of optimized configurable processors from ...